TSMC and ASML announced an industry collaboration on September 8 to move the photomasks used in High NA EUV lithography from the current 6-inch format to 12 inches. The stated goals are straightforward: raise tool throughput, cut chip manufacturing costs, and eliminate stitching constraints.
The roadmap has three milestones. In 2030, TSMC plans to bring High NA into high-volume manufacturing for advanced nodes. In 2031, a 12-inch mask pilot line is expected to be established. By 2033, 12-inch High NA lithography systems are targeted to enter advanced-node production.
What the stitching limit actually is
The technical starting point is that High NA tools expose a field that is half the size of the previous generation's.
Raising the numerical aperture to 0.55 delivers finer resolution, but the trade-off is that a single exposure covers half the area. That barely matters for something like a smartphone SoC, but it's a real problem for AI accelerators, whose die area often approaches or exceeds the mask's exposure limit: the chip has to be split into two sections, exposed separately, and stitched back together. Stitching introduces alignment error and complicates both design and yield.
A 12-inch mask enlarges the usable area, effectively pushing that limit further out. ASML President and CEO Christophe Fouquet framed the path as a gradual one in the announcement:
"We expect High NA EUV adoption to gradually increase, first using existing 6-inch masks, followed by further support from 12-inch masks."
TSMC Chairman and CEO C.C. Wei's comments focused more on the collaboration itself — broadly, that when the industry pools its efforts to solve a complex problem, it can unlock possibilities no single company could reach alone.
How the economics work
Switching mask sizes isn't as simple as swapping a piece of glass. The mask blanks, writing tools, inspection and repair equipment, reticle pods, and the transport mechanisms inside the tool all need to be rebuilt for the new format — which is why the pilot line isn't expected until 2031.
The savings show up on two fronts. One is the design and yield cost that disappears once stitching is no longer needed, which matters most for large chips. The other is throughput: the same number of exposures now covers more area, so tool time per wafer drops. Neither ASML nor TSMC has put a number on either figure based on what's public so far.
The stretch to watch is 2030 to 2033 (a rough estimate based on subtracting the two milestones given in the announcement). TSMC says it wants High NA in high-volume production for advanced nodes by 2030, but only 6-inch masks will be available at that point — large-area AI chips will either have to keep stitching or be designed around the size limit. By the time 12-inch systems actually reach production lines, three more years will have passed. During that window, the cost structure of the most expensive chips — training accelerators, large HBM base dies, oversized-die accelerators — won't change because of this collaboration.
For China's domestic supply chain, the significance is more indirect. Once 12-inch masks become the standard for High NA, the bar rises a notch for mask manufacturing, inspection, and repair — segments where localization has already been lagging behind the attention paid to lithography itself.
Sources: ASML press release, CocoLoop, NRC (Netherlands); the three milestones and both quotes follow ASML's announcement, and neither company has disclosed the expected cost savings.