Peking University-linked chip startup Hanxu Technology has unveiled an inference computing architecture it calls uHBM and uLPU. The first-generation uHBM specifies an on-chip weight-readout bandwidth design value of 24TB/s; the companion uLPU targets a 4B-parameter multimodal backbone model, aiming for decode-stage throughput above 2,000 tokens per second.
Founded in August 2023, the company was incubated out of Peking University's Center for Applied Magnetism and is among the earliest teams in China building MRAM-based magnetic computing.
Welding the Weights in Place
Large-model inference splits into two stages, prefill and decode. Prefill is compute-bound; decode is bandwidth-bound. Every time the chip emits a token, it has to move the model's entire weight set from memory into the compute units once — that's the job HBM does on a GPU. The wider the bandwidth, the faster the tokens come out.
Hanxu's approach is to eliminate that move altogether. Model weights sit permanently in a Persistent MRAM array, matrix-vector operations run on the same piece of silicon, and only low-dimensional activation vectors cross the chip boundary. MRAM is non-volatile — weights survive a power cycle and don't need reloading — and by placing compute units right against the storage array, "readout bandwidth" stops being a question of the inter-chip bus and becomes a question of on-chip routing. A figure like 24TB/s isn't something an off-chip bus is going to deliver anytime soon.
A validation chip, SpinPU-ED01, has already come back from the fab. Public materials list 120 MRAM banks and a measured on-chip memory-access bandwidth density of 0.105TB/(mm²·s); the chip has passed third-party testing and 24 hours of continuous stable operation.
The 4B Ceiling
uLPU's performance target is pegged to a 4B-parameter multimodal backbone, and that size isn't arbitrary. Keeping weights resident on-chip only works if the chip can physically hold them, so the MRAM array's capacity directly caps how large a model can run. Rough math: 4B parameters stored at INT8 comes out to roughly 4GB — already close to what a single chip can pack in under current process nodes.
That constraint naturally points the whole approach toward edge devices and smaller models. In Hanxu's published roadmap, the edge form factor pairs with an NPU and targets robotics; the cloud form factor relies on UCIe die-to-die interconnect and 112G/224G SerDes to link multiple chips together, trading stacking for capacity. The roadmap runs from uHBM-Die to uLPU-Chip and Module, then on to a 2U tray and a full rack — a complete path on paper, but every step has to re-solve interconnect loss and heat dissipation from scratch.
Between Design Spec and Silicon
One thing needs to be said plainly: both the 24TB/s figure and the 2,000-tokens/s target are current architectural design values, not measurements from a mass-produced chip. The real answer arrives once the first-generation product comes back from the fab.
That distinction tends to get flattened in narratives around Chinese-made chips. A design value reflects the architecture's ceiling; a measured value reflects what's left once process, yield, and timing closure have all taken their cut — and historically that discount has ranged anywhere from 30% to 70%.
Hanxu's timing isn't bad. HBM production capacity is locked up by a handful of major suppliers, domestic manufacturers are struggling to get allocation, and finding a way around HBM for inference has become a clear demand. Groq already proved one path by swapping SRAM in for HBM, at the cost of small per-card capacity and the need to cluster hundreds or thousands of cards together. MRAM is denser than SRAM, so in theory a single chip can hold more weight — that's where Hanxu's route diverges from Groq's. Whether it can actually deliver still comes down to a chip that hasn't gone into mass production yet.
Sources: Hanxu Technology public technical materials, STAR Market Daily, CocoLoop, Kuaikeji; the uHBM bandwidth design value, decode throughput target, and SpinPU-ED01's bank count and bandwidth density have been checked against public disclosures — bandwidth and throughput are both architectural design values, not measured results.